1. Field of the Invention
The present invention relates to semiconductor computer memories, and more particularly to a redundancy architecture and technique that provides a separate array for word replacement without impacting the size or performance of content-addressable memories (CAM).
2. Background Description
The ability of a memory system to continue correct performance of its tasks after the occurrence of hardware or software faults is highly important. The physical replication of hardware is perhaps the most common technique of providing of fault tolerance used in the memory systems. As semiconductor components of memories have become more densely integrated and increased of capacity, the concept of hardware redundancy has become more common and more practical.
According to the trend of high density of semiconductor devices, redundancy techniques are employed to substitute defect-free memory cells for defective redundant memory cells in order to improve the manufacturing yield of products. At the same time, high-density semiconductor memory devices require division of memory cells into a plurality of blocks containing predetermined memory cells in order to achieve high-speed operation and low power consumption. Since semiconductor memories comprise a matrix of memory cells arranged in rows (word lines) and columns (bit lines), redundant word lines and/or redundant bit lines are provided to functionally replace defective word lines and/or defective bit lines, respectively. Generally, since memory cells in a memory device have relatively more defects in columns, the semiconductor memory devices arrange spare or redundant columns in which redundant memory cells are associated with each block and have used a column redundancy scheme which replaces a normal column containing a defective normal memory cell or cells with a redundant column having defect-free redundant memory cells in the same block. In some high-performance SRAM, a separate redundant array has been used for word line replacement.
Associative memories or content-addressable memories retrieve information on the basis of data content stored rather than addresses. An associative memory performs comparison (i.e., exclusive-OR or equivalent) operations at its bit level. The result of comparison on a group of bits in words in the memory are transmitted to a register called a response register or flag. In general, CAM can be viewed as comprising a number of bit-serial processing elements. Furthermore, the bit-level logic is moved out of the memory part of the processor so that the memory part of the processor comprises a number of random-access memories called word modules. This type of organization of CAM provides a simplicity in design and low cost of an associative processor, but the bit-serial operations slow down the system drastically while the growth in the communication industry is driving the need for larger CAM circuits. Therefore, the area of the CAM increases as well as the probability of a possible defect occurring. Therefore providing redundancy of CAM circuitry is a very important issue. However, the known approaches to provide redundancy in CAM present substantial problems.
Known CAM redundancy techniques generally have used additional redundancy circuitry which takes space on the memory chip. Techniques which have minimized additional circuitry (e.g., use of priority encodes to implement word-line redundancy) typically limit test capability and/or increase the test time. Thus, there is a need for improved architectures and techniques for implementing redundancy in CAM.
In view of foregoing, a new redundancy architecture in a CAM has been invented. This type of redundancy does not increase chip size and allows CAM testing and replacement of defective words by spare elements already provided on the chip. The invention provides improved fault tolerance for semiconductor CAM.
In one aspect, the invention encompasses a content-addressable memory system with a separate array for word redundancy comprising:
a default CAM memory array for storing data;
a redundancy latch;
a redundant CAM memory array containing redundant word-lines;
a redundancy register array for storing at least one respective address of a defective word and for performing the index translation between the redundant array and default memory arrays;
a compare logic, coupled to the redundancy memory array.
In another aspect, the invention encompasses a method of redundancy of word-lines in a content-addressable memory, comprising the step of parallel search of both default and redundant arrays and capturing hit/miss data for each of the word lines in the default CAM array and the redundant CAM arrays.
These and other aspects of the invention are described in further detail below.